1. Field of the Invention
This invention relates to an analogue to digital converter (A/D converter) system.
2. Description of the Prior Art
The present invention relates, in particular, to an A/D converter system which provides adaptive sample timing for digitizing a received stream of information symbols. Ideally, the sampling instant for an analogue to digital converter should be aligned with the centre (or eye) of each successive symbol.
U.S. Pat. No. 4,788,696 describes a decision timing control circuit for controlling the decision timing of an A/D converter. An error rate detector is employed to derive error rate information from the output of the A/D converter. This information is then used for controlling the phase of an A/D converter clock signal thereby to control the decision timing of the A/D converter. The circuit is applied to the field of digital radio communications and is dependent upon a clock signal which is recovered from a demodulated signal by a clock recovery circuit. The circuit described in U.S. Pat. No. 4,788,696, is complicated and, as a result of being based on error rate detection, is relatively slow in operation.
U.S. Pat. No. 4,565,993 describes a dynamic strobe timing circuit for an A/D converter. This converter employs circuitry for receiving information indicative of a recent history of amplitude variation of an analogue signal to logically modify the most significant error bit and to apply this to an integrator. An integrated value is then used to adjust a variable time delay clock circuit for use in determining the detection time for the A/D converter. This circuit is specifically directed to optimising the accuracy of signal detection for a multi-level signal. In operation, it is arranged to detect a slope of the angled signal by comparing the N most significant bits of a present and previous word value. The results of the comparison are integrated to determine a signal which is then used for adjusting the timing of a clock signal for initiating each A/D conversion.
U.S. Pat. No. 5,406,329 describes an A/D converter for converting a sampled image signal from a solid state optical image pick-up to a digital image signal. The circuit described therein employs a test signal generator for generating a test signal which is synchronised with a driving pulse for driving the image pick-up. This test signal is used to control the phase of a first sampling pulse and the phase of a second sampling pulse relative to each other. In a test mode, the output signal of an A/D converter is passed through a delay circuit having a delay of one clock period and a difference between the delayed signal and the non-delayed signal is derived by means of a subtracting circuit in order to determine an absolute difference between black and white levels. In the testing mode, a peak-to-peak value thus obtained is supplied to an integrator for integrating the absolute peak-to-peak values of the test signals. By comparing integrated values during successive horizontal blanking periods, a signal is supplied to a variable delay circuit for adjusting a phase of the sampling pulse for A/D conversion. This circuit is also complicated in construction, and is adapted for a particular purpose using a dedicated test signal.
Although the prior art documents described above provide circuits for adjusting the sampling time for an A/D converter, there remains a need to provide a solution to the determination of the timing of the sampling instant for an A/D converter which is aligned to the centre of each successive symbol of a stream of received information symbols to be digitized, without the need for complex and therefore expensive synchronisation and preferably without the need for the A/D converter to sample more frequently than once per symbol.